1. Field of the Invention
The present invention relates to data output circuits having a latch function of outputting received data at a given timing, and to a semiconductor device such as a memory device equipped with such a data output circuit.
2. Description of the Related Art
Recently, semiconductor devices such as memory devices have been required to operate at higher speeds due to speeding up of microprocessors. Particularly, there has been considerable activity in the development of semiconductor devices which employ a pipeline technique.
The pipeline technique segments a series of processes (in memories, examples of those are address latch, address decode, read of data from cells, transfer of data to an output circuit, and data output) carried out in series into parts. A first process related to a first command is executed. Then, a second process related to the first command is started and simultaneously a first process related to a second command is started. Hence, the speed of processing commands can be increased substantially.
Normally, the pipeline technique is directed to segmenting a plurality of processes which are to be serially executed into parts so that the times it takes to execute these parts are equal to each other. Latch circuits are provided to the output sides of processing circuits which execute the segmented parts. However, in practice, semiconductor devices have a difficulty in that latch circuits are provided in positions so that the above processing circuits have an identical processing time.
With the above in mind, the semiconductor devices such as memory devices employ a particular pipeline called wave pipeline, in which data is output at a timing which lags, by a given number of clocks, behind the time when a read command is input (the latency of data output). In the wave pipeline, a pipe is configured by utilizing a propagation in logic circuits. Data latch circuits are provided in the vicinity of the output circuits. In order to operate the wave pipeline at a high speed due to speeding up of the microprocessors, it is necessary to reduce a time delay caused in an data output circuit which has a latch function and a parallel-to-serial conversion function.
FIG. 1 is a circuit diagram of a conventional configuration of a data output circuit provided in a synchronous DRAM device (hereinafter such a device will be referred to as an SDRAM device). The data output circuit shown in FIG. 1 includes an FIFO memory 10 of a pointer type forming a latch circuit, a parallel-to-serial converter circuit (hereinafter this circuit will be referred to as a PS converter circuit)20, and an output part 30. The FIFO memory 10 is connected to data input terminals MDB0, MDB1, MDB2 and MDB3 connected to a data bus extending from a memory core part (an illustration thereof is omitted). The FIFO memory 10 latches input data in parallel formation and outputs the latched input data to the PS converter circuit 20 in order of receipt thereof. The PS converter circuit 20 converts four-bit parallel data into two serial data trains (a 4:2 parallel-to-serial conversion), and outputs these trains to the output part 30. The output part 30 converts the two serial data trains into a single serial data train (a 2:1 parallel-to-serial conversion).
The FIFO memory 10 includes four data latch circuits DLAT0-DLAT4, an input pointer 11 and an output pointer 12. Each of the data latch circuits DLAT0-DLAT4 includes an input transfer gate, latch elements Latch0-Latch3, and an output transfer gate. The input transfer gate is made up of four MOS transistors controlled by the input pointer 11. The output transfer gate is made up of four MOS transistors controlled by the output pointer 12.
The PS converter circuit 20 includes latch elements Latch00-Latch30, Latch22, Latch32, transfer gates formed of transistors, and a parallel-to-serial pointer (hereinafter this pointer will be referred to as a PS pointer) 21. The output part 30 includes latch elements Latch0 and Latch1, an output clock generator 31, an output buffer 32, an output transistor 33 and a data output terminal DQ.
FIG. 2 is a timing chart of an operation of the data output circuit shown in FIG. 1. A read command is received by the semiconductor device having the output circuit shown in FIG. 2, and data "0"-"19" read from the memory core part are transferred over the data bus in synchronism with a data pulse (D-pulse) signal, and are applied to the FIFO memory 10 via data input terminals MDB0-MDB3. The input data are latched in the latches elements Latch0-Latch3 of the data latch circuits DLAT0-DLAT3 in response to control signals pi0-pi3 supplied from the input pointer 11. In FIG. 2, the latch element latch0 of the data latch circuit DLAT0 is indicated as DLAT0.sub.-- L0. For example, in response to the control signal pi0, the latch elements DLAT.sub.-- L0-DLAT3.sub.-- L3 of the data latch circuit DLAT0 latch the input data "0"-"3", respectively. Then, the latched input data are output as Fout0-Fout3 in response to the control signals po1-po3 of the output pointer 12.
In response to a control signal ps0 output by the PS pointer 21 of the PS converter circuit 20, the data Fout0-Fout3 are input to the latch elements Latch00-Latch30, respectively. In response to a control signal ps1, the data in the latch element Latch00 is output as PSout0. In response to a control signal ps2, the data in the latch element Latch10 is output as PSout1, and the respective data latched in the latch elements Latch 20 and Latch30 are transferred to the latch elements Latch22 and Latch32. In response to a control signal ps3, the data in the latch element Latch22 is output as PSout0. In response to the control signal ps0, the data in the latch element Latch32 is output as PSout1. Then, next data are input to the latch elements Latch00-Latch30.
Hence, the output PSout0 has a data train such as "0", "2", "4", . . . , and the output PSout1 has a data train such as "1", "3", "5", . . . . That is, the parallel data Fout0-Fout3 are concerted into two serial data trains PSout0 and PSout1. That is, the 4:1 parallel-to-serial conversion is carried out. Then, the 2:1 parallel-to-serial conversion is implemented by the two transfer gates which control the output timings of the output part 30 in accordance with output timing clocks oclk0 and oclk1 which are generated by the output clock generator 31 and has a complementary relationship. The serial data thus obtained is output to the data output terminal DQ via the output buffer 32 and the output transistor 33. The output clock generator 31 generates the output timing clocks oclk0 and oclk1 from an output enable signal OE and a clock signal, which signals are supplied from the outside of the semiconductor device.
However, the above-mentioned conventional data output circuit has a large time delay due to an arrangement in which the FIFO memory 10 and the PS converter circuit 20 are separately configured and provided, and does not operate at a high speed.